Invention Grant
- Patent Title: Electronic package assembly with compact die placement
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Application No.: US15395985Application Date: 2016-12-30
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Publication No.: US10373888B2Publication Date: 2019-08-06
- Inventor: Eric J. Li , Vipul V. Mehta , Digvijay A. Raorane
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North & Western, LLP
- Agent David W. Osborne
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L25/065

Abstract:
An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.
Public/Granted literature
- US20180190560A1 ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT Public/Granted day:2018-07-05
Information query
IPC分类: