公开(公告)号：US11328968B2

公开(公告)日：2022-05-10

申请号：US16463638

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US11075166B2

公开(公告)日：2021-07-27

申请号：US17005002

申请日：2020-08-27

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10707171B2

公开(公告)日：2020-07-07

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita Yoshihiro ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20170179041A1

公开(公告)日：2017-06-22

申请号：US14978897

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Eric J. Li ,  Joshua D. Heppner

IPC: H01L23/552 ,  H01L23/29 ,  H01L23/528 ,  H01L21/56 ,  H01L21/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/768

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic component or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The vertical portions of the EMI shielding, including EMI shielding on the periphery may be formed by filling conductive ink in trenches formed in-situ with curing the molding. The top portion of the EMI shielding and the may additionally be cured conductive ink.

公开(公告)号：US11955434B2

公开(公告)日：2024-04-09

申请号：US17861125

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US11676900B2

公开(公告)日：2023-06-13

申请号：US15778398

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Nitin Deshpande ,  Shawna M. Liff ,  Omkar Karhade ,  Amram Eitan ,  Timothy A. Gosselin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/36 ,  H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

公开(公告)号：US10256205B2

公开(公告)日：2019-04-09

申请号：US15812754

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20190096838A1

公开(公告)日：2019-03-28

申请号：US16198429

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US09953929B2

公开(公告)日：2018-04-24

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US20170186699A1

公开(公告)日：2017-06-29

申请号：US14998089

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Yoshihiro Tomita ,  Nachiket R. Raravikar ,  Robert L. Sankman

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H04M1/02 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683 ,  H01L21/311 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/15311 ,  H01L2924/1815

Abstract: Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package.