Invention Grant
- Patent Title: Memory architecture including response manager for error correction circuit
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Application No.: US15798916Application Date: 2017-10-31
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Publication No.: US10379937B2Publication Date: 2019-08-13
- Inventor: Om Ranjan , Riccardo Gemelli , Abhishek Gupta
- Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l.
- Applicant Address: NL Schiphol IT Agrate Brianza
- Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee Address: NL Schiphol IT Agrate Brianza
- Agency: Crowe & Dunlevy
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G06F3/06

Abstract:
A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
Public/Granted literature
- US20190129790A1 MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION CIRCUIT Public/Granted day:2019-05-02
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