Memory architecture including response manager for error correction circuit

    公开(公告)号:US10860415B2

    公开(公告)日:2020-12-08

    申请号:US16454365

    申请日:2019-06-27

    摘要: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

    Memory architecture including response manager for error correction circuit

    公开(公告)号:US10379937B2

    公开(公告)日:2019-08-13

    申请号:US15798916

    申请日:2017-10-31

    IPC分类号: G06F11/00 G06F11/10 G06F3/06

    摘要: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

    MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION CIRCUIT

    公开(公告)号:US20190129790A1

    公开(公告)日:2019-05-02

    申请号:US15798916

    申请日:2017-10-31

    IPC分类号: G06F11/10 G06F3/06

    摘要: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.