Invention Grant
- Patent Title: Performing a cyclic redundancy checksum operation responsive to a user-level instruction
-
Application No.: US15589561Application Date: 2017-05-08
-
Publication No.: US10379938B2Publication Date: 2019-08-13
- Inventor: Steven R. King , Frank L. Berry , Michael E. Kounavis
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: H03M13/09
- IPC: H03M13/09 ; G06F11/10 ; G06F9/30 ; G06F15/76 ; H03M13/00 ; G06T1/20 ; H03M13/15
Abstract:
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Public/Granted literature
- US20170242746A1 PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION Public/Granted day:2017-08-24
Information query
IPC分类:
