Invention Grant
- Patent Title: Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block
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Application No.: US15681183Application Date: 2017-08-18
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Publication No.: US10381103B2Publication Date: 2019-08-13
- Inventor: Christopher Morzano , Sujeet Ayyapureddi
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.
Public/Granted literature
- US20190057758A1 APPARATUSES AND METHODS FOR LATCHING REDUNDANCY REPAIR ADDRESSES AT A MEMORY Public/Granted day:2019-02-21
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