公开(公告)号：US10443531B2

公开(公告)日：2019-10-15

申请号：US15681143

申请日：2017-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Morzano

IPC: G11C29/00 ,  F02D41/24 ,  G11C29/02 ,  G06F12/06 ,  G11C17/16 ,  G11C29/44

Abstract: Apparatuses and methods for storing redundancy repair information for memories are disclosed. An example apparatus includes a fuse array, a repair plane, and a decode logic and control circuit. The fuse array stores repair information that includes repair commands and load repair addresses. The load repair addresses include a respective repair address. The repair plane includes a block of memory and repair logic. The block of memory includes a plurality of redundant memory and the repair logic includes a plurality of repair blocks. Each repair block is associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks stores a repair address. The decode logic and control circuit reads the repair information and decodes the repair commands, and loads repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands.

公开(公告)号：US20190055895A1

公开(公告)日：2019-02-21

申请号：US15681143

申请日：2017-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Morzano

IPC: F02D41/24 ,  G11C29/02 ,  G06F12/06

CPC classification number: F02D41/249 ,  G06F12/0653 ,  G11C17/16 ,  G11C29/027 ,  G11C29/787 ,  G11C2029/4402

Abstract: Apparatuses and methods for storing redundancy repair information for memories are disclosed. An example apparatus includes a fuse array, a repair plane, and a decode logic and control circuit. The fuse array stores repair information that includes repair commands and load repair addresses. The load repair addresses include a respective repair address. The repair plane includes a block of memory and repair logic. The block of memory includes a plurality of redundant memory and the repair logic includes a plurality of repair blocks. Each repair block is associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks stores a repair address. The decode logic and control circuit reads the repair information and decodes the repair commands, and loads repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands.

公开(公告)号：US11015547B2

公开(公告)日：2021-05-25

申请号：US16407029

申请日：2019-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Morzano

IPC: G11C29/00 ,  F02D41/24 ,  G11C29/02 ,  G06F12/06 ,  G11C17/16 ,  G11C29/44 ,  G06F12/02

Abstract: Apparatuses and methods for storing redundancy repair information for memories are disclosed. An example apparatus includes a fuse array, a repair plane, and a decode logic and control circuit. The fuse array stores repair information that includes repair commands and load repair addresses. The load repair addresses include a respective repair address. The repair plane includes a block of memory and repair logic. The block of memory includes a plurality of redundant memory and the repair logic includes a plurality of repair blocks. Each repair block is associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks stores a repair address. The decode logic and control circuit reads the repair information and decodes the repair commands, and loads repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands.

公开(公告)号：US20250095718A1

公开(公告)日：2025-03-20

申请号：US18788001

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Christopher Morzano

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

公开(公告)号：US20190264629A1

公开(公告)日：2019-08-29

申请号：US16407029

申请日：2019-05-08

Applicant: Micron Technology , Inc.

Inventor： Christopher Morzano

IPC: F02D41/24 ,  G11C29/00 ,  G11C29/02 ,  G06F12/06

Abstract: Apparatuses and methods for storing redundancy repair information for memories are disclosed. An example apparatus includes a fuse array, a repair plane, and a decode logic and control circuit. The fuse array stores repair information that includes repair commands and load repair addresses. The load repair addresses include a respective repair address. The repair plane includes a block of memory and repair logic. The block of memory includes a plurality of redundant memory and the repair logic includes a plurality of repair blocks. Each repair block is associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks stores a repair address. The decode logic and control circuit reads the repair information and decodes the repair commands, and loads repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands.

公开(公告)号：US10381103B2

公开(公告)日：2019-08-13

申请号：US15681183

申请日：2017-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Morzano ,  Sujeet Ayyapureddi

IPC: G11C29/00

Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.

公开(公告)号：US20190057758A1

公开(公告)日：2019-02-21

申请号：US15681183

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Christopher Morzano ,  Sujeet Ayyapureddi

IPC: G11C29/00

CPC classification number: G11C29/765 ,  G11C29/72 ,  G11C29/785

Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.