公开(公告)号：US20250166682A1

公开(公告)日：2025-05-22

申请号：US18916640

申请日：2024-10-15

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C8/12 ,  G11C5/02

Abstract: A semiconductor device is presented. The semiconductor device includes a first memory mat associated with a first memory array segment and a first portion of a second memory array segment, a second memory mat disposed adjacent to the first memory mat, the second memory mat associated with a second portion of the second memory array segment and a first portion of a third memory array segment, and a third memory mat disposed adjacent to the second memory mat and on an opposite side to the first memory mat in the semiconductor device, the third memory mat associated with a second portion of the third memory array segment and a fourth memory array segment.

公开(公告)号：US20250123924A1

公开(公告)日：2025-04-17

申请号：US18743994

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10

Abstract: Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.

公开(公告)号：US20250077424A1

公开(公告)日：2025-03-06

申请号：US18745843

申请日：2024-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/06

Abstract: Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US12119043B2

公开(公告)日：2024-10-15

申请号：US17898737

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Sujeet Ayyapureddi ,  Yang Lu ,  Amitava Majumdar

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40618

Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

公开(公告)号：US12111727B2

公开(公告)日：2024-10-08

申请号：US18167768

申请日：2023-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/4063

CPC classification number: G06F11/1068 ,  G11C11/40615 ,  G11C11/4063

Abstract: A memory may perform a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit may count errors which are detected, and set a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

公开(公告)号：US20240281390A1

公开(公告)日：2024-08-22

申请号：US18410808

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Dong Uk Lee ,  Sujeet Ayyapureddi ,  Lingming Yang ,  Tyler J. Gomm

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory device includes a stack of eight memory dies having an 8N architecture and a stack of four memory dies having a 4N architecture. A first half and a second half of the stack of eight memory dies can each include 32 channels divided equally across the first half of dies and across the second half of dies. Banks of each of the 32 channels on the first half of dies can be associated with respective first pseudo channels. Banks of each of the 32 channels on the second half of dies can be associated with respective second pseudo channels. The stack of four memory dies can include the 32 channels divided equally amongst the dies, and the banks of each of the 32 channels on the stack of four memory dies can be divided equally across the respective first and second pseudo channels.

公开(公告)号：US12019513B2

公开(公告)日：2024-06-25

申请号：US17730381

申请日：2022-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/106

Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

公开(公告)号：US20240161859A1

公开(公告)日：2024-05-16

申请号：US18504353

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G11C29/52 ,  G11C7/10 ,  G11C7/12 ,  G11C29/00

CPC classification number: G11C29/52 ,  G11C7/1096 ,  G11C7/12 ,  G11C29/785

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

公开(公告)号：US20240071550A1

公开(公告)日：2024-02-29

申请号：US17822912

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G11C2207/10

Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.