- Patent Title: Lithographacally defined vias for organic package substrate scaling
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Application No.: US15745701Application Date: 2015-09-25
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Publication No.: US10381291B2Publication Date: 2019-08-13
- Inventor: Adel A. Elsherbini , Henning Braunisch , Brandon M. Rawlings , Aleksandar Aleksov , Feras Eid , Javier Soto
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/052460 WO 20150925
- International Announcement: WO2017/052647 WO 20170330
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/48 ; H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
Public/Granted literature
- US20180233431A1 LITHOGRAPHACALLY DEFINED VIAS FOR ORGANIC PACKAGE SUBSTRATE SCALING Public/Granted day:2018-08-16
Information query
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