Invention Grant
- Patent Title: PCI express tunneling over a multi-protocol I/O interconnect
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Application No.: US15942922Application Date: 2018-04-02
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Publication No.: US10387348B2Publication Date: 2019-08-20
- Inventor: David J. Harriman , Maxim Dan
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F13/38
- IPC: G06F13/38 ; G06F13/40 ; G06F13/42

Abstract:
Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
Public/Granted literature
- US20180357195A1 PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT Public/Granted day:2018-12-13
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