Invention Grant
- Patent Title: Interposer, semiconductor package structure, and semiconductor process
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Application No.: US15818337Application Date: 2017-11-20
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Publication No.: US10388598B2Publication Date: 2019-08-20
- Inventor: Wen-Long Lu , Min Lung Huang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/498 ; H01L21/48 ; H01L21/683
Abstract:
A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
Public/Granted literature
- US20180076122A1 INTERPOSER, SEMICONDUCTOR PACKAGE STRUCTURE, AND SEMICONDUCTOR PROCESS Public/Granted day:2018-03-15
Information query
IPC分类:
