The present disclosure provides a semiconductor device including a substrate, an n− type layer, an n+ type region, a p type region, a p+ type region, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode, wherein the n+ type region is disposed at a left side and a right side of the n− type layer in a plan view and configured to form in a striped pattern in a plan view, wherein the p+ type region is disposed at an outer surface of the n+ type region in a plan view and configured to form in a striped pattern in a plan view, wherein the p type region is disposed at an inner surface the n+ type region in a plan view and is separated by a predetermined interval along a longitudinal direction of the n+ type region in a plan view.