- Patent Title: Slot/sub-slot prefetch architecture for multiple memory requestors
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Application No.: US15899138Application Date: 2018-02-19
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Publication No.: US10394718B2Publication Date: 2019-08-27
- Inventor: Kai Chirca , Joseph R. M. Zbiciak , Matthew D. Pierson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Kenneth Liu; Charles A. Brill; Frank D. Cimino
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0897 ; G06F12/0811 ; G06F12/0862 ; G06F12/0886 ; G06F9/38

Abstract:
A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
Public/Granted literature
- US20180239710A1 SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS Public/Granted day:2018-08-23
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