Invention Grant
- Patent Title: Technologies for scalable hierarchical interconnect topologies
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Application No.: US15279830Application Date: 2016-09-29
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Publication No.: US10394738B2Publication Date: 2019-08-27
- Inventor: Mario Flajslik , Eric R. Borch , Michael A. Parker , Wayne A. Downer
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F13/40
- IPC: G06F13/40

Abstract:
Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.
Public/Granted literature
- US20180089127A1 TECHNOLOGIES FOR SCALABLE HIERARCHICAL INTERCONNECT TOPOLOGIES Public/Granted day:2018-03-29
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