Invention Grant
- Patent Title: Event specific page faults for interrupt handling
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Application No.: US15818123Application Date: 2017-11-20
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Publication No.: US10402343B2Publication Date: 2019-09-03
- Inventor: Manohar R. Castelino , John Hinman
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F13/32 ; G06F12/1009 ; G06F12/08

Abstract:
Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.
Public/Granted literature
- US20180143910A1 EVENT SPECIFIC PAGE FAULTS FOR INTERRUPT HANDLING Public/Granted day:2018-05-24
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