Invention Grant
- Patent Title: System, apparatus and method for selective enabling of locality-based instruction handling
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Application No.: US15475249Application Date: 2017-03-31
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Publication No.: US10409727B2Publication Date: 2019-09-10
- Inventor: Berkin Akin , Rajat Agarwal , Jong Soo Park , Christopher J. Hughes , Chiachen Chou
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0888 ; G06F12/0811 ; G06F12/04 ; G06F12/0831 ; G06F12/0886

Abstract:
In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
Public/Granted literature
- US20180285280A1 System, Apparatus And Method For Selective Enabling Of Locality-Based Instruction Handling Public/Granted day:2018-10-04
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