Invention Grant
- Patent Title: Semiconductor package with cavity
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Application No.: US15639077Application Date: 2017-06-30
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Publication No.: US10410940B2Publication Date: 2019-09-10
- Inventor: Praneeth Akkinepally
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/13 ; H01L23/522 ; H01L23/00 ; H01L23/538 ; H01L25/10 ; H01L25/16

Abstract:
An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.
Public/Granted literature
- US20190006252A1 Semiconductor Package with Cavity Public/Granted day:2019-01-03
Information query
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