- 专利标题: Semiconductor device and method of manufacturing the same
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申请号: US15847103申请日: 2017-12-19
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公开(公告)号: US10411036B2公开(公告)日: 2019-09-10
- 发明人: Yoshiki Yamamoto
- 申请人: Renesas Electronics Corporation
- 申请人地址: JP Tokyo
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Shapiro, Gabor and Rosenberger, PLLC
- 优先权: JP2013-116265 20130531
- 主分类号: H01L27/12
- IPC分类号: H01L27/12 ; H01L21/84 ; H01L21/762 ; H01L27/11 ; H01L29/78
摘要:
A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
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