公开(公告)号：US10559595B2

公开(公告)日：2020-02-11

申请号：US16005615

申请日：2018-06-11

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto

IPC分类号： H01L27/12 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10

摘要： A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.

公开(公告)号：US10461158B2

公开(公告)日：2019-10-29

申请号：US16150323

申请日：2018-10-03

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US10411036B2

公开(公告)日：2019-09-10

申请号：US15847103

申请日：2017-12-19

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L27/11 ,  H01L29/78

摘要： A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.

公开(公告)号：US10263078B2

公开(公告)日：2019-04-16

申请号：US15925850

申请日：2018-03-20

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC分类号： H01L21/00 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/265 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234

摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US10056406B2

公开(公告)日：2018-08-21

申请号：US14924527

申请日：2015-10-27

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hideki Makiyama ,  Yoshiki Yamamoto

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L27/1207 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66545

摘要： The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

公开(公告)号：US09935125B2

公开(公告)日：2018-04-03

申请号：US13859297

申请日：2013-04-09

申请人： Renesas Electronics Corporation

发明人： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20150111348A1

公开(公告)日：2015-04-23

申请号：US14579242

申请日：2014-12-22

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC分类号： H01L29/66 ,  H01L21/265

CPC分类号： H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

摘要翻译： 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US11152393B2

公开(公告)日：2021-10-19

申请号：US16520966

申请日：2019-07-24

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L27/11 ,  H01L29/78

摘要： A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.

公开(公告)号：US10411121B2

公开(公告)日：2019-09-10

申请号：US16100908

申请日：2018-08-10

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L29/51 ,  H01L27/11563 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11568 ,  H01L27/11573

摘要： The reliability of a semiconductor device is improved. A first insulating film and a protective film are formed on a semiconductor substrate. The first insulating film and the protective film of a first region are selectively removed, and an insulating film is formed on the exposed semiconductor substrate. In a state where the first insulating film in a second region, a third region, and a fourth region is covered with the protective film, the semiconductor substrate is heat-treated in an atmosphere containing nitrogen, thereby introducing nitrogen to the interface between the semiconductor substrate and the second insulating film in the first region. In other words, a nitrogen introduction point is formed on the interface between the semiconductor substrate and the second insulating film. In this configuration, the protective film acts as an anti-nitriding film.

公开(公告)号：US09754661B2

公开(公告)日：2017-09-05

申请号：US15264450

申请日：2016-09-13

申请人： Renesas Electronics Corporation

发明人： Yoshiki Yamamoto

IPC分类号： G11C11/00 ,  G11C11/419 ,  H01L29/06 ,  H01L23/528 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0692

摘要： A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an element isolation region overlying the main surface; a first and a second active region located in the n-type well region and surrounded by the element isolation region; an insulating film overlying the main surface in the first active region; a semiconductor layer overlying the insulating film; a gate electrode layer overlying the semiconductor layer through a gate insulating film; a p-type source and a drain region formed in the semiconductor layer at both ends of the gate electrode layer; a dummy gate electrode layer overlying the semiconductor layer through the gate insulating film; an n-type semiconductor region overlying an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.