- Patent Title: Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption
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Application No.: US14803896Application Date: 2015-07-20
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Publication No.: US10430191B2Publication Date: 2019-10-01
- Inventor: Yevgeniy M. Astigeyevich , Dmitry M. Maslennikov , Sergey P. Scherbinin , Marat Zakirov , Pavel G. Matveyev , Andrey Rodchenko , Andrey Chudnovets , Boris V. Shurygin
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley Flight & Zimmerman, LLC
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/32 ; G06F8/41

Abstract:
Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a strand including a fork instruction introducing a first speculative assumption. A basing instruction to initialize a basing value of the strand before execution of a first instruction under the first speculative assumption. A determination of whether a second instruction under a second speculative assumption modifies a first memory address that is also modified by the first instruction under the first speculative assumption is made. The second instruction is not modified when the second instruction does not modify the first memory address. The second instruction is modified based on the basing value when the second instruction modifies the first memory address, the basing value to cause the second instruction to modify a second memory address different from the first memory address.
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