Invention Grant
- Patent Title: Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device
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Application No.: US15436963Application Date: 2017-02-20
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Publication No.: US10431630B2Publication Date: 2019-10-01
- Inventor: Philippe Boivin , Jean-Jacques Fagot
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1658405 20160909
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L21/762 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L45/00 ; H01L21/28

Abstract:
A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
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Information query
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