Invention Grant
- Patent Title: Apparatuses and methods for shielded memory architecture
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Application No.: US15691055Application Date: 2017-08-30
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Publication No.: US10446502B2Publication Date: 2019-10-15
- Inventor: Ferdinando Bedeschi , Umberto Di Vincenzo , Daniele Vimercati
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron, Technology, Inc.
- Current Assignee: Micron, Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L23/528 ; H01L27/108 ; H01L27/11507 ; G11C11/22 ; G11C11/4091 ; G11C11/409 ; G11C11/16 ; G11C11/408 ; G11C11/4094 ; G11C13/00 ; G11C7/10 ; G11C7/08
Abstract:
Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.
Public/Granted literature
- US20190067206A1 APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE Public/Granted day:2019-02-28
Information query
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