Invention Grant
- Patent Title: Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures
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Application No.: US14953574Application Date: 2015-11-30
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Publication No.: US10446670B2Publication Date: 2019-10-15
- Inventor: Bruce B. Doris , Hong He , Junli Wang , Nicolas J. Loubet
- Applicant: International Business Machines Corporation , STMicroelectronics, Inc.
- Applicant Address: US NY Armonk US TX Coppell
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.
- Current Assignee Address: US NY Armonk US TX Coppell
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/66 ; H01L29/78 ; H01L27/092 ; H01L29/10 ; H01L29/165 ; H01L29/423 ; H01L21/265 ; H01L21/8238

Abstract:
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
Public/Granted literature
- US20160218215A1 INTEGRATION OF STRAINED SILICON GERMANIUM PFET DEVICE AND SILICON NFET DEVICE FOR FINFET STRUCTURES Public/Granted day:2016-07-28
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