Invention Grant
- Patent Title: High-electron-mobility transistors with heterojunction dopant diffusion barrier
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Application No.: US15755489Application Date: 2015-09-25
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Publication No.: US10446685B2Publication Date: 2019-10-15
- Inventor: Chandra S. Mohapatra , Matthew V. Metz , Harold W. Kennel , Gilbert Dewey , Willy Rachmady , Anand S. Murthy , Jack T. Kavalieros , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard, & Mughal LLP
- International Application: PCT/US2015/052302 WO 20150925
- International Announcement: WO2017/052609 WO 20170330
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/02 ; H01L29/10 ; H01L27/092 ; H01L29/778

Abstract:
III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
Public/Granted literature
- US20180248028A1 HIGH-ELECTRON-MOBILITY TRANSISTORS WITH HETEROJUNCTION DOPANT DIFFUSION BARRIER Public/Granted day:2018-08-30
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