Invention Grant
- Patent Title: Preemptive cache writeback with transaction support
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Application No.: US15718564Application Date: 2017-09-28
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Publication No.: US10452548B2Publication Date: 2019-10-22
- Inventor: David A. Roberts , Elliot H. Mednick
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/0804
- IPC: G06F12/0804 ; G06F12/0811 ; G06F12/0831 ; G06F12/084 ; G06F12/0891 ; G06F12/126

Abstract:
A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.
Public/Granted literature
- US20190095330A1 PREEMPTIVE CACHE WRITEBACK WITH TRANSACTION SUPPORT Public/Granted day:2019-03-28
Information query
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