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    INPUT/OUTPUT STUTTER WAKE ALIGNMENT
    1.
    发明公开
    INPUT/OUTPUT STUTTER WAKE ALIGNMENT 审中-公开

    公开(公告)号：US20240004721A1

    公开(公告)日：2024-01-04

    申请号：US17853294

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

    IPC: G06F9/50

    CPC classification number: G06F9/5083 ,  G06F9/5038 ,  G06F9/5033 ,  G06F9/5016

    Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.

    DYNAMIC, VARIABLE BIT-WIDTH NUMERICAL PRECISION ON FPGAS FOR MACHINE LEARNING TASKS
    2.
    发明申请
    DYNAMIC, VARIABLE BIT-WIDTH NUMERICAL PRECISION ON FPGAS FOR MACHINE LEARNING TASKS 审中-公开

    公开(公告)号：US20190171420A1

    公开(公告)日：2019-06-06

    申请号：US15833287

    申请日：2017-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya ,  Elliot H. Mednick

    IPC: G06F7/57 ,  G06N3/04 ,  G06F7/544 ,  H03K19/177

    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.

    HYBRID ANALOG-DIGITAL FLOATING POINT NUMBER REPRESENTATION AND ARITHMETIC
    3.
    发明申请
    HYBRID ANALOG-DIGITAL FLOATING POINT NUMBER REPRESENTATION AND ARITHMETIC 审中-公开

    公开(公告)号：US20190102175A1

    公开(公告)日：2019-04-04

    申请号：US15843965

    申请日：2017-12-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Elliot H. Mednick ,  David John Cownie

    IPC: G06F9/30 ,  G06F7/483

    Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.

    Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks
    4.
    发明授权
    Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks 有权

    公开(公告)号：US11216250B2

    公开(公告)日：2022-01-04

    申请号：US15833287

    申请日：2017-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya ,  Elliot H. Mednick

    IPC: G06F7/57 ,  G06N3/04 ,  H03K19/17728 ,  G06N3/08 ,  G06N3/063 ,  G06F7/544

    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.

    Virtual FPGA management and optimization system
    7.
    发明授权
    Virtual FPGA management and optimization system 有权

    公开(公告)号：US10164639B1

    公开(公告)日：2018-12-25

    申请号：US15812411

    申请日：2017-11-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Andrew G. Kegel ,  Elliot H. Mednick

    IPC: H03K19/177 ,  G06F17/50 ,  G06F15/78

    Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

    Method of task transition between heterogenous processors
    8.
    发明授权
    Method of task transition between heterogenous processors 有权

    公开(公告)号：US11586472B2

    公开(公告)日：2023-02-21

    申请号：US16709404

    申请日：2019-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

    IPC: G06F9/50 ,  G06F11/30

    Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.

    Hybrid analog-digital floating point number representation and arithmetic
    9.
    发明授权
    Hybrid analog-digital floating point number representation and arithmetic 有权

    公开(公告)号：US10289413B2

    公开(公告)日：2019-05-14

    申请号：US15843965

    申请日：2017-12-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Elliot H. Mednick ,  David John Cownie

    IPC: G06F9/30 ,  G06F7/483

    Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.

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