Invention Grant
- Patent Title: Segmented erase in memory
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Application No.: US14922611Application Date: 2015-10-26
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Publication No.: US10453535B2Publication Date: 2019-10-22
- Inventor: Shantanu R. Rajwade , Akira Goda , Pranav Kalavade , Krishna K. Parat , Hiroyuki Sanda
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/16 ; G11C16/08 ; G11C16/34

Abstract:
Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.
Public/Granted literature
- US20170117049A1 SEGMENTED ERASE IN MEMORY Public/Granted day:2017-04-27
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