公开(公告)号：US10453535B2

公开(公告)日：2019-10-22

申请号：US14922611

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/34

Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

公开(公告)号：US10128262B2

公开(公告)日：2018-11-13

申请号：US14998251

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： Randy J. Koval ,  Hiroyuki Sanda

IPC: H01L27/115 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565

Abstract: An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.

公开(公告)号：US20170117049A1

公开(公告)日：2017-04-27

申请号：US14922611

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0441 ,  G11C16/0458 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C16/3477

Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

公开(公告)号：US09424936B1

公开(公告)日：2016-08-23

申请号：US14666147

申请日：2015-03-23

Applicant: Intel Corporation

Inventor： Toru Tanzawa ,  Akira Goda ,  Shigekazu Yamada ,  Hiroyuki Sanda

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for providing an apparatus comprising a memory array, to which bias voltage may be provided to reduce leakage current. In one embodiment, the apparatus may comprise a three-dimensional (3D) memory array having at least first and second blocks; and circuitry coupled with the 3D memory array to access the 3D memory array. The circuitry may include circuit to deselect the first block and select the second block, and supply a first bias voltage to the deselected first block and a second bias voltage to the selected second block, to reduce leakage current in the 3D memory array. The first bias voltage may be different than the second bias voltage. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于提供包括存储器阵列的装置的技术和配置，可以提供偏置电压以减少泄漏电流。 在一个实施例中，该装置可以包括具有至少第一和第二块的三维（3D）存储器阵列; 以及与3D存储器阵列耦合以访问3D存储器阵列的电路。 电路可以包括用于取消选择第一块并选择第二块的电路，并将第一偏置电压提供给未选择的第一块，并将第二偏置电压提供给所选择的第二块，以减少3D存储器阵列中的漏电流。 第一偏置电压可以不同于第二偏置电压。 可以描述和/或要求保护其他实施例。