- Patent Title: Facilitation of orthotopic patterns during substrate fabrication
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Application No.: US15439723Application Date: 2017-02-22
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Publication No.: US10459334B2Publication Date: 2019-10-29
- Inventor: Barton G. Lane
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/66 ; G03F1/42 ; G03F7/20

Abstract:
Described herein are technologies to facilitate the fabrication of substrates, such as semiconductor wafers. More particularly, technologies described herein facilitate the correct placement of patterns of lines and spaces on a substrate. The resulting patterned substrate is the product of photolithography process and/or the pattern transference (e.g., etching) that occurs during the fabrication of substrates (e.g., semiconductor wafers). The scope of the present invention is pointed out in the appending claims.
Public/Granted literature
- US20180240720A1 FACILITATION OF ORTHOTOPIC PATTERNS DURING SUBSTRATE FABRICATION Public/Granted day:2018-08-23
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