Invention Grant
- Patent Title: Methods and apparatus to perform region formation for a dynamic binary translation processor
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Application No.: US15721456Application Date: 2017-09-29
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Publication No.: US10474442B2Publication Date: 2019-11-12
- Inventor: Girish Venkatasubramanian , Tanima Dey , Dasarath Weeratunge , Cristiano Pereira , Jose Baiocchi Paredes
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F8/41

Abstract:
Methods, apparatus, systems and articles of manufacture to perform region formation for usage by a dynamic binary translation are disclosed. An example apparatus includes an initial region former to form an initial region starting at a first block of hot code of a control flow graph. The initial region former also adds blocks of hot code lying on a first hottest path of the control flow graph. A region extender extends the initial region to form an extended region including the initial region. The extended region begins at a hottest exit of the initial region and includes blocks of hot code lying on a second hottest path until one of a threshold path length has been satisfied or a back edge of the control flow graph is added to the extended region. A region pruner prunes the remove all loop nests except a selected loop nest which forms a final region.
Public/Granted literature
- US20190102150A1 METHODS AND APPARATUS TO PERFORM REGION FORMATION FOR A DYNAMIC BINARY TRANSLATION PROCESSOR Public/Granted day:2019-04-04
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