公开(公告)号：US20160283247A1

公开(公告)日：2016-09-29

申请号：US14668605

申请日：2015-03-25

申请人： Intel Corporation

发明人： Girish Venkatasubramanian ,  Ethan Schuchman ,  David Keppel ,  Sebastian Winkel ,  David N. Mackintosh ,  Jaroslaw Topp

IPC分类号： G06F9/38

CPC分类号： G06F9/30087 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/455 ,  G06F9/45516 ,  G06F9/4552

摘要： Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

摘要翻译： 与选择性地执行提交指令有关的方法和装置。 在一个实施例中，数据存储装置存储当硬件处理器执行时硬件处理器执行以下操作的代码：将指令转换成由硬件处理器执行的转换指令，标记提交指令以执行和 用于硬件处理器的可选执行，并且包括用于可选执行标记的提交指令的提示; 以及硬件提交单元，用于基于提示来确定标记为可选执行的提交指令是否被执行。

公开(公告)号：US20160085556A1

公开(公告)日：2016-03-24

申请号：US14494829

申请日：2014-09-24

申请人： Intel Corporation

发明人： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC分类号： G06F9/38

CPC分类号： G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

摘要： A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

摘要翻译： 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。

公开(公告)号：US10474442B2

公开(公告)日：2019-11-12

申请号：US15721456

申请日：2017-09-29

申请人： Intel Corporation

发明人： Girish Venkatasubramanian ,  Tanima Dey ,  Dasarath Weeratunge ,  Cristiano Pereira ,  Jose Baiocchi Paredes

IPC分类号： G06F9/30 ,  G06F8/41

摘要： Methods, apparatus, systems and articles of manufacture to perform region formation for usage by a dynamic binary translation are disclosed. An example apparatus includes an initial region former to form an initial region starting at a first block of hot code of a control flow graph. The initial region former also adds blocks of hot code lying on a first hottest path of the control flow graph. A region extender extends the initial region to form an extended region including the initial region. The extended region begins at a hottest exit of the initial region and includes blocks of hot code lying on a second hottest path until one of a threshold path length has been satisfied or a back edge of the control flow graph is added to the extended region. A region pruner prunes the remove all loop nests except a selected loop nest which forms a final region.

公开(公告)号：US10191745B2

公开(公告)日：2019-01-29

申请号：US15475389

申请日：2017-03-31

申请人： Intel Corporation

发明人： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC分类号： G06F9/45 ,  G06F9/30

摘要： In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US09916164B2

公开(公告)日：2018-03-13

申请号：US14737058

申请日：2015-06-11

申请人： Intel Corporation

发明人： Vineeth Mekkat ,  Girish Venkatasubramanian ,  Howard H. Chen

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/45

CPC分类号： G06F9/3861 ,  G06F8/41 ,  G06F8/443 ,  G06F9/30058 ,  G06F9/3846

摘要： Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.

公开(公告)号：US09858057B2

公开(公告)日：2018-01-02

申请号：US14956671

申请日：2015-12-02

申请人： Intel Corporation

发明人： Girish Venkatasubramanian ,  Chaitanya Mangla ,  Gerolf F. Hoflehner ,  Ethan Schuchman

IPC分类号： G06F9/45 ,  G06F11/07 ,  G06F11/30 ,  G06F9/455 ,  F01D5/08 ,  F02C7/18 ,  G06F9/445 ,  G06F11/34

CPC分类号： G06F8/447 ,  F01D5/082 ,  F02C7/18 ,  F05D2250/38 ,  F05D2260/14 ,  F05D2260/941 ,  G06F8/51 ,  G06F8/52 ,  G06F9/44589 ,  G06F9/4552 ,  G06F11/0751 ,  G06F11/30 ,  G06F11/3003 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  Y10T29/49 ,  Y10T29/49995

摘要： Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.

公开(公告)号：US20180285113A1

公开(公告)日：2018-10-04

申请号：US15475389

申请日：2017-03-31

申请人： Intel Corporation

发明人： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC分类号： G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/3016

摘要： In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US10083033B2

公开(公告)日：2018-09-25

申请号：US14643855

申请日：2015-03-10

申请人： INTEL CORPORATION

发明人： Sebastian Winkel ,  Girish Venkatasubramanian ,  Tyler N. Sondag ,  Rolf Kassa

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

公开(公告)号：US20160364240A1

公开(公告)日：2016-12-15

申请号：US14737058

申请日：2015-06-11

申请人： Intel Corporation

发明人： Vineeth Mekkat ,  Girish Venkatasubramanian ,  Howard H. Chen

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F8/41 ,  G06F8/443 ,  G06F9/30058 ,  G06F9/3846

摘要： Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.

摘要翻译： 本文公开了方法，装置，系统和制品。 示例性设备包括指令分析器，用于识别要由硬件处理器执行的指令内的预测块。 示例性装置包括：性能监视器，用于基于与所述预测块相关联的指令地址来访问误差预测统计量。 示例性装置包括区域形成器，响应于确定误差预测统计量高于误差预测阈值，将所述预测块包括在用于优化的预测区域中。

公开(公告)号：US09274799B1

公开(公告)日：2016-03-01

申请号：US14494829

申请日：2014-09-24

申请人： Intel Corporation

发明人： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC分类号： G06F9/45 ,  G06F9/38

CPC分类号： G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

摘要： A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

摘要翻译： 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。