- 专利标题： Integration of III-V devices on Si wafers
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申请号： US15492785申请日： 2017-04-20
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公开(公告)号： US10475888B2公开(公告)日： 2019-11-12
- 发明人: Sansaptak Dasgupta , Han Wui Then , Seung Hoon Sung , Sanaz K. Gardner , Marko Radosavljevic , Benjamin Chu-Kung , Robert S. Chau
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt, P.C.
- 主分类号： H01L29/20
- IPC分类号： H01L29/20 ; H01L29/04 ; H01L29/06 ; H01L29/66 ; H01L21/308 ; H01L21/02
摘要：
An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
公开/授权文献
- US20170221999A1 INTEGRATION OF III-V DEVICES ON SI WAFERS 公开/授权日：2017-08-03
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