公开(公告)号：US12125888B2

公开(公告)日：2024-10-22

申请号：US16642861

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/41725 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US12027613B2

公开(公告)日：2024-07-02

申请号：US16419179

申请日：2019-05-22

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC分类号： H01L29/778 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L29/20 ,  H01L29/51

CPC分类号： H01L29/7786 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0655 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/778 ,  H01L2224/0401 ,  H01L2924/13064

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

公开(公告)号：US11715790B2

公开(公告)日：2023-08-01

申请号：US16390819

申请日：2019-04-22

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L21/02 ,  H01L29/808 ,  H01L29/10

CPC分类号： H01L29/7786 ,  H01L21/0254 ,  H01L21/02458 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/49 ,  H01L29/4925 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/808 ,  H01L29/1066

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

公开(公告)号：US11575036B2

公开(公告)日：2023-02-07

申请号：US16651327

申请日：2017-09-28

申请人： Intel Corporation

发明人： Han Wui Then ,  Stephan Leuschner ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L21/285 ,  H01L21/765 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H03F3/21 ,  H03F3/45

摘要： Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

公开(公告)号：US11527532B2

公开(公告)日：2022-12-13

申请号：US16419240

申请日：2019-05-22

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L29/778 ,  H01L25/065

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.

公开(公告)号：US11508812B2

公开(公告)日：2022-11-22

申请号：US16643446

申请日：2017-09-29

申请人： Intel Corporation

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Pavel M. Agababov

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L21/02

摘要： Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

公开(公告)号：US20220320350A1

公开(公告)日：2022-10-06

申请号：US17848275

申请日：2022-06-23

申请人： Intel Corporation

发明人： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

摘要： A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US11430873B2

公开(公告)日：2022-08-30

申请号：US16147707

申请日：2018-09-29

申请人： Intel Corporation

发明人： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC分类号： H01L29/40 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423

摘要： A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

公开(公告)号：US20220216149A1

公开(公告)日：2022-07-07

申请号：US17700198

申请日：2022-03-21

申请人： Intel Corporation

发明人： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Richard Farrington Vreeland ,  Sansaptak Dasgupta

IPC分类号： H01L23/522 ,  H01L23/532

摘要： Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

公开(公告)号：US11342232B2

公开(公告)日：2022-05-24

申请号：US16016415

申请日：2018-06-22

申请人： Intel Corporation

发明人： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L27/02 ,  H01L29/872 ,  H01L21/02 ,  H01L29/778

摘要： A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.