Invention Grant
- Patent Title: SM4 acceleration processors, methods, systems, and instructions
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Application No.: US16147650Application Date: 2018-09-29
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Publication No.: US10476667B2Publication Date: 2019-11-12
- Inventor: Shay Gueron , Vlad Krasnov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE, LLP
- Main IPC: H04L29/06
- IPC: H04L29/06 ; H04L9/06 ; G06F9/30 ; G06F21/60

Abstract:
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.
Public/Granted literature
- US20190109705A1 SM4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Public/Granted day:2019-04-11
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