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114 条记录 (耗时 0.032 秒)

    Secure memory
    1.
    发明授权
    Secure memory 有权

    公开(公告)号：US11586560B2

    公开(公告)日：2023-02-21

    申请号：US17165361

    申请日：2021-02-02

    申请人： Intel Corporation

    发明人： Rodrigo R. Branco ,  Shay Gueron

    IPC分类号： G06F12/14 ,  H04L9/06 ,  G06F11/10 ,  G06F21/78 ,  G06F7/58

    摘要： Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data storage device. The read request may comprise address data indicating a first address of a first storage location at the data storage device. The storage controller may request from the data storage device a first encrypted data unit stored at the first memory element and a first encrypted set of parity bits, such as Error Correction Code (ECC) bits, associated with the first storage location. An encryption system may decrypt the first encrypted set of parity bits to generate a first set of parity bits based at least in part on an a first location parity key for the first address.

    SM3 hash algorithm acceleration processors, methods, systems, and instructions
    2.
    发明授权
    SM3 hash algorithm acceleration processors, methods, systems, and instructions 有权

    公开(公告)号：US11075746B2

    公开(公告)日：2021-07-27

    申请号：US16847626

    申请日：2020-04-13

    申请人： Intel Corporation

    发明人： Shay Gueron ,  Vlad Krasnov

    IPC分类号： G06F21/00 ,  H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G09C1/00 ,  G06F21/72

    摘要： A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

    Vector operations with operand base system conversion and re-conversion
    7.
    发明授权
    Vector operations with operand base system conversion and re-conversion 有权

    公开(公告)号：US09965276B2

    公开(公告)日：2018-05-08

    申请号：US15141786

    申请日：2016-04-28

    申请人： Intel Corporation

    发明人： Shay Gueron ,  Vlad Krasnov

    IPC分类号： G06F17/16 ,  G06F9/30 ,  G06F7/544 ,  G06F7/53

    CPC分类号： G06F9/30036 ,  G06F7/5324 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30025 ,  G06F9/30098 ,  G06F9/3016 ,  G06F17/16

    摘要： Methods and apparatuses relating to vector operations with operand base system conversion and re-conversion are described. In one embodiment, a method includes executing a single instruction by receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system, converting the vector elements into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector, performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result, accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system, and converting contents of the register into the first base system.

    Technologies for modifying a first cryptographic cipher with operations of a second cryptographic cipher
    9.
    发明授权
    Technologies for modifying a first cryptographic cipher with operations of a second cryptographic cipher 有权

    公开(公告)号：US09800406B2

    公开(公告)日：2017-10-24

    申请号：US14283955

    申请日：2014-05-21

    申请人： Intel Corporation

    发明人： Shay Gueron

    IPC分类号： H04L9/08 ,  H04L9/14 ,  H04L9/06

    CPC分类号： H04L9/0838 ,  H04L9/06 ,  H04L9/14 ,  H04L2209/24

    摘要： Generally, the present disclosure provides technology modifying a first cryptographic cipher with one or more operations of a second cryptographic cipher. In some embodiments the technology leverages a mathematical relationship between representations of data used in the first and second ciphers to enable the substitution of one or more operations of the first cipher with one or more operations of the second cipher. The resulting modified cipher may in some instances exhibit improved performance and or security, relative to the unmodified first cipher. Methods, computer readable media, and apparatus including or utilizing the technologies are also described.