Invention Grant
- Patent Title: Integrated error checking and correction (ECC) in byte mode memory devices
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Application No.: US15911068Application Date: 2018-03-02
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Publication No.: US10482947B2Publication Date: 2019-11-19
- Inventor: Christopher E. Cox , Uksong Kang , Nagi Aboulenein
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10 ; G11C11/408 ; G11C29/52

Abstract:
A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.
Public/Granted literature
- US20180254079A1 INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY DEVICES Public/Granted day:2018-09-06
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