Invention Grant
- Patent Title: Memory devices including a word line defect detection circuit
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Application No.: US16014222Application Date: 2018-06-21
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Publication No.: US10482973B2Publication Date: 2019-11-19
- Inventor: Jae-Yun Lee , Joon Soo Kwon , Byung Soo Kim , Sang-Soo Park , Il Han Park , Jong-Hoon Lee
- Applicant: Samsung Electronics Co. Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel, P.A.
- Priority: KR10-2017-0151619 20171114
- Main IPC: G11C16/12
- IPC: G11C16/12 ; H03K5/135 ; G11C16/16 ; G11C16/32 ; G11C8/08 ; G11C16/08 ; H03K3/011 ; G11C16/30 ; G11C5/14 ; G11C7/22 ; G11C16/04

Abstract:
A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.
Public/Granted literature
- US20190147961A1 MEMORY DEVICES INCLUDING A WORD LINE DEFECT DETECTION CIRCUIT Public/Granted day:2019-05-16
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