公开(公告)号：US10854250B2

公开(公告)日：2020-12-01

申请号：US15997964

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Joon Soo Kwon ,  Byung Soo Kim ,  Su-Yong Kim ,  Sang-Soo Park ,  Il Han Park ,  Kang-Bin Lee ,  Jong-Hoon Lee ,  Na-Young Choi

IPC: G11C8/08 ,  G11C29/12 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C5/14 ,  G11C16/12 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

公开(公告)号：US09570168B2

公开(公告)日：2017-02-14

申请号：US14832229

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/418 ,  G11C11/417 ,  G11C7/10

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。

公开(公告)号：US20160055905A1

公开(公告)日：2016-02-25

申请号：US14832229

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。

公开(公告)号：US10482973B2

公开(公告)日：2019-11-19

申请号：US16014222

申请日：2018-06-21

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jae-Yun Lee ,  Joon Soo Kwon ,  Byung Soo Kim ,  Sang-Soo Park ,  Il Han Park ,  Jong-Hoon Lee

IPC: G11C16/12 ,  H03K5/135 ,  G11C16/16 ,  G11C16/32 ,  G11C8/08 ,  G11C16/08 ,  H03K3/011 ,  G11C16/30 ,  G11C5/14 ,  G11C7/22 ,  G11C16/04

Abstract: A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.

公开(公告)号：US09659644B2

公开(公告)日：2017-05-23

申请号：US14612640

申请日：2015-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Jeong ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Jae-Yun Lee

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.

公开(公告)号：US20140022831A1

公开(公告)日：2014-01-23

申请号：US13945418

申请日：2013-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Young Kim ,  Min-Gu Kang ,  Jae-Yun Lee ,  Beak-Hyung Cho

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18

Abstract: A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

Abstract translation: 半导体存储器件包括多个功能位线，至少一个虚拟位线和虚拟位线选择单元。 至少一个虚拟位线与功能位线的最外位线相邻。 所述虚拟位线选择单元响应于与所述至少一个虚拟位线不相邻的所述多个功能位线之一的选择控制信号来激活所述至少一个虚拟位线。 半导体存储器件可以确保照相余量，使得功能位线的图案尺寸可以均匀。

公开(公告)号：US09336877B2

公开(公告)日：2016-05-10

申请号：US14504914

申请日：2014-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yun Lee ,  Sun Woo-Jung ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C8/08 ,  G11C13/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C13/0026 ,  G11C13/004 ,  G11C2211/5623 ,  G11C2213/71

Abstract: A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.

Abstract translation: 非易失性存储器件利用可变电阻元件。 非易失性存储器件包括多个存储体，并且布置成跨越多个存储体的第一至第三写入全局位线。 多个存储体中的每一个包括使用电阻材料的多个非易失性存储单元。 第一，第二和第三写全局位线按顺序彼此直接相邻布置。 当在写入周期期间向第一写入全局位线提供写入电流时，固定的电压被施加到第二写入全局位线，而第三个全局位线被浮置。

公开(公告)号：US09147440B2

公开(公告)日：2015-09-29

申请号：US13945418

申请日：2013-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Young Kim ,  Min-Gu Kang ,  Jae-Yun Lee ,  Beak-Hyung Cho

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18

Abstract: A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

Abstract translation: 半导体存储器件包括多个功能位线，至少一个虚拟位线和虚拟位线选择单元。 至少一个虚拟位线与功能位线的最外位线相邻。 所述虚拟位线选择单元响应于与所述至少一个虚拟位线不相邻的所述多个功能位线之一的选择控制信号来激活所述至少一个虚拟位线。 半导体存储器件可以确保照相余量，使得功能位线的图案尺寸可以均匀。