Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
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Application No.: US16016862Application Date: 2018-06-25
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Publication No.: US10483170B2Publication Date: 2019-11-19
- Inventor: De-Wei Yu , Chia Ping Lo , Liang-Gi Yao , Weng Chang , Yee-Chia Yeo , Ziwei Fang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/268 ; H01L21/324 ; H01L21/8234 ; H01L21/8238 ; H01L29/66

Abstract:
A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.
Public/Granted literature
- US20180308765A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION Public/Granted day:2018-10-25
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