Invention Grant
- Patent Title: SRAM cell with balanced write port
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Application No.: US16047586Application Date: 2018-07-27
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Publication No.: US10522553B2Publication Date: 2019-12-31
- Inventor: Kuo-Hsiu Hsu , Yu-Kuan Lin , Feng-Ming Chang , Lien Jung Hung , Ping-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L27/092 ; G11C11/419 ; G11C11/412 ; G11C11/413

Abstract:
A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.
Public/Granted literature
- US20180366469A1 SRAM Cell with Balanced Write Port Public/Granted day:2018-12-20
Information query
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