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    Method and Structure for Gate-All-Around Devices with Deep S/D Contacts
    1.
    发明申请
    Method and Structure for Gate-All-Around Devices with Deep S/D Contacts 有权

    公开(公告)号：US20230063098A1

    公开(公告)日：2023-03-02

    申请号：US17462634

    申请日：2021-08-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin

    IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

    摘要： A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.

    Cut Metal Gate in Memory Macro Edge and Middle Strap
    4.
    发明申请
    Cut Metal Gate in Memory Macro Edge and Middle Strap 有权

    公开(公告)号：US20210313463A1

    公开(公告)日：2021-10-07

    申请号：US17352587

    申请日：2021-06-21

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

    IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762

    摘要： A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

    Semiconductor Device with Dual Isolation Liner and Method of Forming the Same
    5.
    发明申请
    Semiconductor Device with Dual Isolation Liner and Method of Forming the Same 有权

    公开(公告)号：US20210265224A1

    公开(公告)日：2021-08-26

    申请号：US16801576

    申请日：2020-02-26

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yu-Kuan Lin

    IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L27/092

    摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate having a first region and a second region; a first semiconductor fin formed on the substrate within the first region; a second semiconductor fin formed on the substrate within the second region; a first liner layer disposed along a lower portion of the first semiconductor fin and a lower portion of the second semiconductor fin; a second liner layer disposed over the first liner layer in the second region, wherein the second liner layer is different from the first liner layer in composition; and an isolation feature disposed on the first liner layer in the first region and on the second liner layer in the second region, and separating lower portions of the first semiconductor fin and the second semiconductor fin.

    Metal Gate Contacts and Methods of Forming the Same
    7.
    发明申请
    Metal Gate Contacts and Methods of Forming the Same 有权

    公开(公告)号：US20210098471A1

    公开(公告)日：2021-04-01

    申请号：US17012530

    申请日：2020-09-04

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chih-Hsuan Chen ,  Jui-Lin Chen ,  Yu-Kuan Lin

    IPC分类号： H01L27/11 ,  H01L21/768 ,  H01L23/522

    摘要： A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.

    SRAM cell with balanced write port
    8.
    发明授权
    SRAM cell with balanced write port 有权

    公开(公告)号：US10522553B2

    公开(公告)日：2019-12-31

    申请号：US16047586

    申请日：2018-07-27

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC分类号： H01L27/11 ,  H01L27/092 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

    摘要： A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.