中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.022 seconds)

    Fin-Based Well Straps For Improving Memory Macro Performance
    4.
    发明申请
    Fin-Based Well Straps For Improving Memory Macro Performance 有权

    公开(公告)号：US20220367481A1

    公开(公告)日：2022-11-17

    申请号：US17874463

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

    IPC: H01L27/11

    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

    Four-Poly-Pitch SRAM Cell with Backside Metal Tracks
    5.
    发明申请
    Four-Poly-Pitch SRAM Cell with Backside Metal Tracks 有权

    公开(公告)号：US20210375883A1

    公开(公告)日：2021-12-02

    申请号：US16888269

    申请日：2020-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

    IPC: H01L27/11 ,  G11C8/08 ,  G11C7/12

    Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

    Strap cell design for static random access memory (SRAM) array
    6.
    发明授权
    Strap cell design for static random access memory (SRAM) array 有权

    公开(公告)号：US10854279B2

    公开(公告)日：2020-12-01

    申请号：US16921156

    申请日：2020-07-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hao Pao ,  Kian-Long Lim ,  Feng-Ming Chang ,  Lien-Jung Hung

    IPC: G11C11/412 ,  H01L27/11 ,  H01L27/02 ,  H01L27/12 ,  H01L29/78 ,  H01L27/092

    Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.

    Fin-Based Strap Cell Structure for Improving Memory Performance
    7.
    发明申请
    Fin-Based Strap Cell Structure for Improving Memory Performance 审中-公开

    公开(公告)号：US20200251476A1

    公开(公告)日：2020-08-06

    申请号：US16529380

    申请日：2019-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Feng-Ming Chang ,  Chia-Hao Pao ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC: H01L27/11 ,  H01L23/535

    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.

    Strap cell design for static random access memory (SRAM) array
    8.
    发明授权
    Strap cell design for static random access memory (SRAM) array 有权

    公开(公告)号：US10515687B2

    公开(公告)日：2019-12-24

    申请号：US15962409

    申请日：2018-04-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hao Pao ,  Kian-Long Lim ,  Feng-Ming Chang ,  Lien-Jung Hung

    IPC: G11C11/412 ,  H01L27/11 ,  H01L27/02 ,  H01L29/78

    Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array, a second bit cell array, and a strap cell. The second bit cell array is arranged along a first direction. The strap cell is arranged along a second direction and is positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes an H-shaped NW region, an H-shaped PW region, and a deep N-type well (DNW) region. The H-shaped NW region and the H-shaped PW region each includes two strip portions extending along the first direction and a linking portion extending along the second direction. Two terminals of the linking portion are in contact with the two strip portions.

    Static random access memory
    9.
    发明授权
    Static random access memory 有权

    公开(公告)号：US09831250B2

    公开(公告)日：2017-11-28

    申请号：US15059039

    申请日：2016-03-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wen-Chun Keng ,  Feng-Ming Chang

    IPC: H01L27/11 ,  H01L29/78

    CPC classification number: H01L27/1104 ,  H01L29/7827

    Abstract: A static random access memory (SRAM) cell includes first through fourth source diffusion regions sequentially arranged in a first direction, a first pass-gate transistor, a source region of which is formed by the first source diffusion region, first and second pull-up transistors, source regions of which are formed by the second source diffusion region, first and second pull-down transistors, source regions of which are formed by the third source diffusion region, a second pass-gate transistor, a source region of which is formed by the fourth source diffusion region, and an intermediate region between the first and second pass-gate transistors linearly extending along a direction parallel to the first direction and across the entire SRAM cell. Each of the first source diffusion region and the fourth source diffusion region is spaced-apart from the intermediate region.

Patent Agency Ranking