- 专利标题: Circuit place and route optimization based on path-based timing analysis
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申请号: US15793622申请日: 2017-10-25
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公开(公告)号: US10534878B1公开(公告)日: 2020-01-14
- 发明人: Geng Bai , Chao-Yung Wang , Ping-San Tzeng
- 申请人: Avatar Integrated Systems, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Avatar Integrated Systems, Inc.
- 当前专利权人: Avatar Integrated Systems, Inc.
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Van Pelt, Yi & James LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G01R31/28
摘要:
A graph-based analysis (GBA) output is obtained comprising timing information pertaining to a plurality of paths in an integrated circuit. A path-based analysis (PBA) is performed on the GBA output to analyze timing of the plurality of paths and generate a set of improved timing results; wherein the physical measurements used by the PBA are more accurate than the physical measurements used by the GBA. The PBA result is output to an optimizer to automatically adjust the circuit.
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