公开(公告)号：US10691854B1

公开(公告)日：2020-06-23

申请号：US16231311

申请日：2018-12-21

申请人： Avatar Integrated Systems, Inc.

发明人： Chao-Yung Wang ,  Zhong Chen ,  Geng Bai ,  Ping-San Tzeng

IPC分类号： G06F30/3312 ,  G06F30/327

摘要： A set of multi-corner multimode (MCMM) databases that correspond to a set of working scenarios are accessed. A full timing update on the set of MCMM databases, for the set of working scenarios, is applied. A graph based analysis (GBA) timing calibration is performed on the databases, for the set of working scenarios to obtain a set of GBA-calibrated databases. Multiphase optimizations on the set of GBA-calibrated databases are iteratively performed to generate a set of optimized databases, including: performing a phase-specific optimization on the set of GBA-calibrated database to obtain an improved set of databases, and recalibrating GBA timing on the set of improved databases prior to a next phase-specific optimization.

公开(公告)号：US10296700B1

公开(公告)日：2019-05-21

申请号：US15793643

申请日：2017-10-25

申请人： Avatar Integrated Systems, Inc.

发明人： Geng Bai ,  Chao-Yung Wang ,  Ping-San Tzeng

IPC分类号： G06F17/50 ,  G06F17/30 ,  G06F16/28 ,  G06F16/901

摘要： A plurality of multi-corner multimode (MCMM) databases are accessed, wherein at least one of the plurality of MCMM databases corresponds to a first optimization scenario, and at least one of the plurality of MCMM databases corresponds to a second optimization scenario. A first optimization move is performed on paths in the first optimization scenario. The first optimization move is verified using GBA on paths in the second optimization scenario to determine that the first optimization move does not cause timing violations outside an MCMM database associated with the first optimization scenario.

公开(公告)号：US10534883B1

公开(公告)日：2020-01-14

申请号：US15793640

申请日：2017-10-25

申请人： Avatar Integrated Systems, Inc.

发明人： Geng Bai ,  Chao-Yung Wang ,  Ping-San Tzeng

IPC分类号： G06F17/50 ,  G06F16/23 ,  G06F16/2458

摘要： A database is constructed based on a batch PBA performed on a plurality of paths of an integrated circuit. A local PBA is performed on a portion of a selected path. A selected optimization move is identified on the portion of the selected path, based on a result of the local PBA that best meets a set of constraints. A path-wide PBA is performed for an updated path that is based on the selected path incorporating the selected optimization move. The selected optimization move is committed in a netlist associated with the integrated circuit.

公开(公告)号：US10534878B1

公开(公告)日：2020-01-14

申请号：US15793622

申请日：2017-10-25

申请人： Avatar Integrated Systems, Inc.

发明人： Geng Bai ,  Chao-Yung Wang ,  Ping-San Tzeng

IPC分类号： G06F17/50 ,  G01R31/28

摘要： A graph-based analysis (GBA) output is obtained comprising timing information pertaining to a plurality of paths in an integrated circuit. A path-based analysis (PBA) is performed on the GBA output to analyze timing of the plurality of paths and generate a set of improved timing results; wherein the physical measurements used by the PBA are more accurate than the physical measurements used by the GBA. The PBA result is output to an optimizer to automatically adjust the circuit.

公开(公告)号：US10853553B1

公开(公告)日：2020-12-01

申请号：US16434624

申请日：2019-06-07

申请人： Avatar Integrated Systems, Inc.

发明人： Ping-San Tzeng ,  Mingsheng Han ,  Yucheng Wang

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L23/522 ,  G06F115/10

摘要： Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.

公开(公告)号：US10776554B1

公开(公告)日：2020-09-15

申请号：US16100097

申请日：2018-08-09

申请人： Avatar Integrated Systems, Inc.

发明人： Ping-San Tzeng ,  Mingsheng Han

IPC分类号： G06F30/394 ,  G06F30/327 ,  G06F30/398 ,  G06F111/20

摘要： A placed netlist is routed. A circuit is obtained that implements the placed netlist. A net in the circuit is identified to be enhanced. Space adjacent to a wire associated with the net that would accommodate a parallel wire is reserved.