Invention Grant
- Patent Title: Semiconductor die having edge with multiple gradients and method for forming the same
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Application No.: US15725558Application Date: 2017-10-05
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Publication No.: US10535554B2Publication Date: 2020-01-14
- Inventor: Yu-Sheng Tang , Fu-Chen Chang , Cheng-Lin Huang , Chun-Yen Lo , Wen-Ming Chen , Kuo-Chio Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: CN Hsinchu, Taiwan
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: CN Hsinchu, Taiwan
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/522 ; H01L21/304 ; H01L21/56 ; H01L21/768 ; H01L21/683 ; H01L21/67 ; H01L23/00 ; H01L23/48 ; H01L21/78 ; H01L23/498 ; H01L25/10 ; H01L23/58 ; H01L25/065 ; H01L25/00
Abstract:
A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.
Public/Granted literature
- US20180166328A1 SEMICONDUCTOR DIE HAVING EDGE WITH MULTIPLE GRADIENTS AND METHOD FOR FORMING THE SAME Public/Granted day:2018-06-14
Information query
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