公开(公告)号：US20240096642A1

公开(公告)日：2024-03-21

申请号：US18523457

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L21/321 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76888 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/5329

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11456276B2

公开(公告)日：2022-09-27

申请号：US16995183

申请日：2020-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ling-Wei Li ,  Jung-Hua Chang ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/482

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

公开(公告)号：US11004728B2

公开(公告)日：2021-05-11

申请号：US16741078

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chun-Yen Lo ,  Kuo-Chio Liu

IPC: H01L23/544 ,  H01L23/28 ,  H01L21/78 ,  H01L23/495 ,  H01L23/522 ,  H01L21/304 ,  H01L21/768 ,  H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.

公开(公告)号：US11532577B2

公开(公告)日：2022-12-20

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

公开(公告)号：US11088108B2

公开(公告)日：2021-08-10

申请号：US16454350

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yao Yang ,  Ling-Wei Li ,  Yu-Jui Wu ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Lieh-Chuan Chen ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

公开(公告)号：US20200373264A1

公开(公告)日：2020-11-26

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

公开(公告)号：US20200350209A1

公开(公告)日：2020-11-05

申请号：US16933676

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen

IPC: H01L21/82 ,  H01L23/00 ,  H01L21/268 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

公开(公告)号：US09748156B1

公开(公告)日：2017-08-29

申请号：US15180264

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Shen Yeh ,  Cheng-Lin Huang ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Wen-Yi Lin ,  Ming-Chih Yew ,  Yu-Huan Chen ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/18 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/18 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

公开(公告)号：US11854826B2

公开(公告)日：2023-12-26

申请号：US17869150

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L21/321 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76888 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5329 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/83005

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11569159B2

公开(公告)日：2023-01-31

申请号：US16893119

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Wei Li ,  Jung-Hua Chang ,  Cheng-Lin Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.