Invention Grant
- Patent Title: Gain and memory error estimation in a pipeline analog to digital converter
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Application No.: US16249225Application Date: 2019-01-16
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Publication No.: US10541700B2Publication Date: 2020-01-21
- Inventor: Srinivas Kumar Reddy Naru , Narasimhan Rajagopal , Shagun Dusad , Viswanathan Nagarajan , Visvesvaraya Appala Pentakota
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Priority: IN201841009007 20180312
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/04 ; H03M1/16

Abstract:
In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
Public/Granted literature
- US20190280703A1 GAIN AND MEMORY ERROR ESTIMATION IN A PIPELINE ANALOG TO DIGITAL CONVERTER Public/Granted day:2019-09-12
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