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公开(公告)号：US20240120932A1
公开(公告)日：2024-04-11
申请号：US18527355
申请日：2023-12-03
发明人： Yabo NI , Yong ZHANG , Xiaofeng SHEN , Ting LI , Lu LIU , Can ZHU , Jiahao PENG , Liang LI , Dongbing FU , Jianan WANG
CPC分类号： H03M1/164 , H03M1/1038 , H03M1/38
摘要： Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.
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公开(公告)号：US11936398B2
公开(公告)日：2024-03-19
申请号：US17041630
申请日：2019-03-26
CPC分类号： H03M1/164 , G01S7/52023 , G04F10/005 , H03M1/50 , H04B11/00 , H03M3/30
摘要： The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.
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公开(公告)号：US20240048148A1
公开(公告)日：2024-02-08
申请号：US18349636
申请日：2023-07-10
发明人： Martin Kinyua , Eric Soenen
CPC分类号： H03M1/145 , H03M1/0612 , H03M1/164
摘要： An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.
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公开(公告)号：US11451731B2
公开(公告)日：2022-09-20
申请号：US16908980
申请日：2020-06-23
发明人： Jahyun Koo , Hyeokjong Lee
IPC分类号： H04N5/3745 , H01L27/146 , H03M1/16 , H04N5/378 , H03M1/12 , H03M1/56 , H04N5/357 , H04N5/347 , H04N5/376 , H04N5/374
摘要： An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.
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公开(公告)号：US11355184B2
公开(公告)日：2022-06-07
申请号：US16986812
申请日：2020-08-06
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Vipin Tiwari
摘要： Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.
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公开(公告)号：US20220158649A1
公开(公告)日：2022-05-19
申请号：US17410382
申请日：2021-08-24
发明人： PAN ZHANG , KAI-YIN LIU , SHIH-HSIUNG HUANG , WEI-JYUN WANG
摘要： A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.
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公开(公告)号：US11303294B2
公开(公告)日：2022-04-12
申请号：US17086949
申请日：2020-11-02
发明人： Gavin McVeigh
摘要： The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.
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公开(公告)号：US11303292B2
公开(公告)日：2022-04-12
申请号：US17120438
申请日：2020-12-14
发明人： Martin Kinyua , Eric Soenen
摘要： An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.
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公开(公告)号：US11271579B2
公开(公告)日：2022-03-08
申请号：US16333189
申请日：2018-03-01
发明人： Yong Zhang , Ting Li , Zheng-Bo Huang , Ya-Bo Ni , Dong-Bing Fu
摘要： The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.
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10.发明授权公开(公告)号：US11218158B1
公开(公告)日：2022-01-04
申请号：US17154138
申请日：2021-01-21
发明人： Sharvil Pradeep Patil , Donald W. Paterson , Prawal Man Shrestha , Asha Ganesan , Yue Yin , Zhao Li , Victor Kozlov , Hajime Shibata
摘要： In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.
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