- 专利标题: Multi-level history buffer for transaction memory in a microprocessor
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申请号: US15597394申请日: 2017-05-17
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公开(公告)号: US10545765B2公开(公告)日: 2020-01-28
- 发明人: Brian D. Barrick , Steven J. Battle , Joshua W. Bowman , Hung Q. Le , Dung Q. Nguyen , David R. Terry , Albert J. Van Norstrand, Jr.
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Patterson + Sheridan, LLP
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/30 ; G06F9/42 ; G06F9/46 ; G06F9/52
摘要:
Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.
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