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公开(公告)号：US11068274B2
公开(公告)日：2021-07-20
申请号：US15843982
申请日：2017-12-15
发明人： Kenneth L. Ward , Susan E. Eisen , Dung Q. Nguyen , Albert J. Van Norstrand, Jr. , Glenn O. Kincaid , Christopher M. Mueller
摘要： A simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.
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公开(公告)号：US10831492B2
公开(公告)日：2020-11-10
申请号：US16028177
申请日：2018-07-05
发明人： Salma Ayub , Glenn O. Kincaid , Christopher M. Mueller , Dung Q. Nguyen , Eula Faye Abalos Tolentino , Albert J. Van Norstrand, Jr. , Kenneth L. Ward
摘要： Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.
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公开(公告)号：US10545765B2
公开(公告)日：2020-01-28
申请号：US15597394
申请日：2017-05-17
发明人： Brian D. Barrick , Steven J. Battle , Joshua W. Bowman , Hung Q. Le , Dung Q. Nguyen , David R. Terry , Albert J. Van Norstrand, Jr.
摘要： Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.
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公开(公告)号：US10909034B2
公开(公告)日：2021-02-02
申请号：US15845757
申请日：2017-12-18
发明人： David R. Terry , Dung Q. Nguyen , Brian W. Thompto , Joshua W. Bowman , Steven J. Battle , Sundeep Chadha , Brian D. Barrick , Albert J. Van Norstrand, Jr.
IPC分类号： G06F12/0804
摘要： Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.
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公开(公告)号：US10884742B2
公开(公告)日：2021-01-05
申请号：US16552665
申请日：2019-08-27
发明人： Sundeep Chadha , Robert A. Cordes , David A. Hrusecky , Hung Q. Le , Jentje Leenstra , Dung Q. Nguyen , Brian W. Thompto , Albert J. Van Norstrand, Jr.
IPC分类号： G06F12/0842 , G06F9/30 , G06F12/0813 , G06F12/0875 , G06F12/0862 , G06F9/38 , G06F13/16 , G06F13/42
摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
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公开(公告)号：US10248555B2
公开(公告)日：2019-04-02
申请号：US15168434
申请日：2016-05-31
摘要： Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.
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公开(公告)号：US10042647B2
公开(公告)日：2018-08-07
申请号：US15193338
申请日：2016-06-27
发明人： Richard J. Eickemeyer , David A. Hrusecky , Elizabeth A. McGlone , Brian W. Thompto , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/38
摘要： Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.
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公开(公告)号：US11144319B1
公开(公告)日：2021-10-12
申请号：US16940433
申请日：2020-07-28
发明人： Steven J. Battle , Susan E. Eisen , Dung Q. Nguyen , Salma Ayub , Albert J. Van Norstrand, Jr. , Kent Li , Kurt A. Feiste , Christian Gerhard Zoellin
摘要： In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.
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公开(公告)号：US10528352B2
公开(公告)日：2020-01-07
申请号：US15064024
申请日：2016-03-08
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0875
摘要： Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.
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公开(公告)号：US10409598B2
公开(公告)日：2019-09-10
申请号：US16014576
申请日：2018-06-21
发明人： Sundeep Chadha , Robert A. Cordes , David A. Hrusecky , Hung Q. Le , Jentje Leenstra , Dung Q. Nguyen , Brian W. Thompto , Albert J. Van Norstrand, Jr.
IPC分类号： G06F12/0842 , G06F9/30 , G06F12/0813 , G06F12/0875 , G06F12/0862 , G06F13/16 , G06F13/42
摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
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